NAAC-Accredited 'A++' - Grade 2(f) & 12(B) status (UGC) |ISO
9001:2015 Certified | FIST Funded (DST) SIRO(DSIR)
UG
PG - VLSI Design
Project Details: 2019 - 2021 (M.E. VLSI Design)
| S.No | Name of the Students | Title of the Project | Project Guide |
|---|---|---|---|
| 1 | AKSHAYA B |
Multipliers-Driven perturbation of coefficient for low power operation in FIR filter |
Dr. R.S.Sabeenian, Prof.J.Harirajkumar |
| 2 | GOWTHAMPRIYA L |
FPGA Implementation of High Speed Random Key Generation Using Chaotic Process for Cryptography Application |
Dr. R.S.Sabeenian, |
| 3 | JOTHI SNEHA M |
Area Efficient Quadrature Amplitude Modulation (QAM) Using Booth Multiplier for Network Applications |
Dr.K.R.KAVITHA |
| 4 | KANMANI C |
A DECISIVE TECHNOLOGY TO PREDICT AND TRACK COVID-19 USING ARTIFICIAL INTELLIGENCE |
Dr.N.SASIREKHA |
| 5 | KAVIYA P |
Diabetic Retinopathy from Fundus Photography in Image Processing |
Dr.T.Shanthi |
| 6 | KAVIYA S |
Competent Impulse Noise Removal Algorithm For Medical Images Using Non-local Mean Filter and LoG Filter |
Dr.R.Gayathri |
| 7 | OBUNGA KENNEDY OCHIENG |
Built-in-Self calibration for I/Q imbalance quadrature modulator |
Dr.K.Manju |
| 8 | SUBA PRIYADHARSINI M |
IMPLEMENTATION OF ISO CHECK FOR EARLY FAILURE DETECTION IN VEHICLE DESIGN USING FPGA |
Dr.B.Thiyaneswaran |
| 9 | VERSNI R |
Implementation of speech command recognition for arithmetic calculations using FPGA |
Dr. R.S.Sabeenian |