NAAC-Accredited 'A++' - Grade 2(f) & 12(B) status (UGC) |ISO
9001:2015 Certified | FIST Funded (DST) SIRO(DSIR)
UG
PG - VLSI Design
PG - Communication Systems
Project Details: 2022 - 2024 (M.E. VLSI Design)
| S.No | Name of the Student | Project Guide | Project title |
|---|---|---|---|
| 1. | M.Aarthi | Dr.S.Vijayalakshmi | Implementation of Multiple Precision Floating-Point operations |
| 2. | S.Arul Jebastin | Dr.K.R.Kavitha | Designing a multipurpose Programmable Digital Delay Timer |
| 3. | A.Farhana Thabassum | Dr.B.Thiruneelakandan | A Reliable 8T SRAM for High-speed searching and logic-in-memory operations using GDI |
| 4. | V.Harshini | Dr.N.Sasireka | Sequential Element design for a low power Clocking System |
| 5. | S.V.Janani | Dr.K.Angurai | Design of MOORE FSM Sequence detector with Improved speed in memory access control using System Verilog |
| 6. | A.Seenivasan | Dr.G.Ravi | Design of MBRBEC Encoderer Using SEC-DED Extended Hamming Code |
| 7. | C.Sri Kiruthika | - | Exploring Ecg Bold Signals for Alzheimer's disease Diagnosis |
| 8. | S.Udhaya kumar | Dr.R.S.Sabeenian | An Efficient APB Protocol Design and System verilog based verification |
| 9. | K.S.Vijaykumar | Dr.R.S.Sabeenian | System Verilog-Based FIFO Design and Verification with Functional Coverage and Assertion |