NAAC-Accredited 'A++' - Grade 2(f) & 12(B) status (UGC) |ISO
9001:2015 Certified | FIST Funded (DST) SIRO(DSIR)

Project Details: 2013 - 2015 (M.E. VLSI Design)
S.No Name Project Title Guided by
1 ABINAYA M Design of fixed width booth multiplier using MLCP in FIR application. (Eldaas Technologies, Bangalore) Dr.K.R.Kashwan
2 ALMAAS FARVEEN N Performance Analysis of tandem master cylinder through testing setup Rig.(WABCO India Ltd, Chennai) Dr.K.R.Kashwan
3 ANITHA SHALINI P Mitigation of energy consumption cost through DLP & PFC Dr.K.R.Kashwan
4 DIVYA BHARATHI M An FPGA based Security system for distributed sensor network Mrs.V.Meenakshi
5 DIVYA DHANALAKSHMI S SOC based implementation of Test for OBC interface.
(ISRO  Satellite Centre, Bangalore)
6 GOWTHAM S Low power double edge triggered flip-flop design based on a signal feed through scheme Mr.J.Harirajkumar
7 HEMAVATHI.M.S Analysis of techniques used in error detection and correction code for multiple bit- cell upset Dr.K.R.Kashwan
8 JAYA MURUGA RAJA AP Illuminance control of a LED lighting network using Back Propagated Neural Network Mrs.V.Meenakshi
9 JEYA PADMINI J Effective power utilization and conservation in smart homes using IoT Dr.K.R.Kashwan
10 KARPAGAMBAL S Analyses of digitally controlled delay loop NAND for glitch free design Mrs.V.Meenakshi
11 KAVIYA M Design of Baugh- Woolley multiplier with Adaptive Hold logic. Mrs.V.Meenakshi
12 KOHILA G Design of the FAM using modified Booth Recoder in Digital Energy Meter Dr. B. Gopi
13 LAKSHMI R Reduced area and high performance multiplier design using fixed width RPR block Mrs.V.Meenakshi
14 LINDAMOL BENNY LIN master controller for alternator control unit
(BOSCH Ltd, Bangalore)
15 MANORANJITHAM.M Low power High speed DRAM architecture using  DETFF Mrs.S.Vijayashaarathi
16 MINU M Automatic voltage regulation for home appliances using power sensor TAG. Dr.K.R.Kashwan
17 MOHANAPRIYA Y An efficient low power L1 data cache using pre-computation logic Mr.J.Harirajkumar
18 MONISA D K Low complexity LDPC decoder for Error Detection and correction in memory.(Eldaas Technologies, Bangalore) Dr.K.R.Kashwan
19 RADHU T A efficient congestion aware adaptive routing technique in DRAM Dr. Jayapoorni
20 RAGAVI M Implementation of VLSI   architecture for reconfigurable RRC filter using graph based technique Mr.J.Harirajkumar
21 SARANYA M Design of FPGA configuration logic block using MTNCL styles Dr.K.R.Kashwan
22 SELVENDRAN V Implementation of autonomous vehicle for tackling dynamic obstacles using ultrasonic sensors Mrs. V. Meenakshi
23 SENTHILKUMARAN K Design of serial multiplier for high performance DSP processor using constant delay logic style.
(ACEIC Design Technologies)
24 SRI AJAY KUMAR A Logical effort for  SCV- based dual mode logic gates Dr. D Jayanthi
25 SULTHANA A Differential 10T TCAM with parallel Pi-sigma match lines Mrs. V. Meenakshi
26 SWATHIKA P D Efficient design of high –order variable digital filters for multi- modulated signals Mr.J.Harirajkumar
27 TAMIL ENIYAN D Efficient fused  architectures  for FFT Processor using Floating Point Arithmetic Mr.J.Harirajkumar
28 THAMARAI T Implementation of three phase panel based SVPWM generator  for DC-AC inverter Dr.K.R.Kashwan
29 VIGNESHKUMAR C High performance multimedia oriented reconfigurable architecture. Mr.J.Harirajkumar
30 YAMUNA S FFT based frequency estimation for speech extraction using Gaussian mixture model Mr.J.Harirajkumar