NAAC-Accredited 'A++' - Grade 2(f) & 12(B) status (UGC) |ISO
9001:2015 Certified | FIST Funded (DST) SIRO(DSIR)
UG
PG - VLSI Design
Project Details: 2016 - 2018 (M.E. VLSI Design)
| S. NO | Name | Project Title | Supervisors |
|---|---|---|---|
| 1 | Arivazhagan R | Modified carry skip adder by novel-hybrid prefix graph of PPA | Mr.J.Hariraj kumar Ms.M.Senthil Vadivu |
| 2 | Arun A | A new data transfer data matrix methodology for IP protection scheme | Dr.K.Anguraj Mr.A.Ayubkhan |
| 3 | Aswini M | Design of SRAM cell using CMOS technology for low power | Dr.N.S.Sasirekha Ms.V.Meenakshi |
| 4 | Gowsalya R | An identification of human using eye sclera blood vessel pattern | Dr.B.Thiyaneswaran Mr.N.S.Yoganathan |
| 5 | Prabha B | Performance analysis of various modulation technique in WIMAX | Ms.A.P.Jayakrishna Ms.S.Vijayasarathi |
| 6 | Sisira Surendran C | VLSI implementation of 5/3 lifting 2d discrete wavelet transform for offline signature verification | Dr.K.R.Kavitha Ms.M.Susaritha |
| 7 | Vinothini Jance S | Improved low power implicit pulse triggered flip flop with reduced power dissipation | Dr.G.Ravi Mr.J.P.Senthilkumar |
| 8 | Balajee M | Realization of high speed 64 bit binary division using pipeline technique | Ms.T.Premakumari Ms.V.Geethalakshmi |