NAAC-Accredited 'A' - Grade 2(f) & 12(B) status (UGC) |ISO
9001:2015 Certified | FIST Funded (DST) SIRO(DSIR)

Project Details: 2014 - 2016 (M.E. VLSI Design)
S.No Name Project Title Guided by
1 Archana M An Efficient Architecture for Improved Reliability of Cache Memory Using Same Tag Bits Dr.K.R.Kashwan
2 Boobalan A Grouped Clock Gated Flip-Flop Array for Low Power Applications  Mrs. V. Meenakshi
3 Deepika S Fault Analysis in Gear Mechanism using Dual-Tree Complex Wavelet Transform Dr.K.R.Kashwan
4 Divya V High Capacity Steganography Technique Based on Wavelet Transform  Mrs. N. Sasirekha
5 Gowrishankar P Design of Carry Propagation Adder Using Hybrid Full adder Circuit Mrs.V.Meenakshi
6 Kayalvizhi E A Modified Low Power Architecture for GOBAR Filter Mrs. N. Sasirekha
7 Manju V Implementation of Fully Automatic Wet Grinder Mrs. S. Jayapoorni
8 Nafeeza S Design of High Performance Asynchronous Pipeline Using Feed through Logic Mrs.V.Meenakshi
9 Nivedha J Implementation of Intelligent Surveillance System Using Adaptive Gamma Correction Method. Mr. G. Ravi
10 Parthipa rani T Implementation Of A Low-Cost High-Performance WSN Based Power Demand using FPGA Controller Mrs.V.Meenakshi
11 Rajam G Design of an Energy Efficient Zigbee System using SEU Hardened Flip-Flops Mrs.V.Meenakshi
12 Rajasekar G High Speed Multi Output Circuits using Adiabatic Logic Dr. D. Jayanthi
13 Ramakrishnan M Design of 8T ROM Embedded SRAM Using Double Word line for Low Power High Speed Application Mrs.V.Meenakshi
14 Ramkumar M Multi Clock Router with Buffered FIFO for Lossless on Chip and Off Chip Communication  Dr. K.R. Kavitha
15 Ramya V. P Design of using SCN Low Power High Speed Modified CAM Mrs.S.Vijayashaarathi
16 Revathi T Design of Vedic Multiplier using QCA Mrs.V.Meenakshi
17 Sanketha M Implementation of Cochlear Implant for Speech Enhancement and Timbre Detection Using Fractional Delay Filter Dr.K.R.Kashwan
18 Saranya K An Implementation of Low  Complexity and Faster Least Mean Square Filter for Noise Cancellation Application Dr.K.R.Kashwan
19 Saranya R Octapod Spider-Gait-Walking Robot Implementation Using Arduino Nano Processor Dr.K.R.Kashwan
20 Saravanakumar.B Adaptive Routing Technology Using Modified SAC and Shortest Path Algorithm Dr.R.Vinodkumar
21 Shamli R Real Time Monitoring of Open Core Protocol Interface for System On Chip Mr.G.Ravi
22 Silviya Sara T Modified Reverse Converter using Hancarlson Structure with Carry Look Ahead Adder Mrs.V.Meenakshi
23 Sowmiya Rajam M FPGA Implementation of Intelligent Human Life Safety System Mrs.V.Meenakshi
24 Suganya B Area Efficient and Low Power Epileptic Seizure Detection Using Effective Algorithms Mrs.V.Meenakshi
25 Suganya R FPGA Based Intelligent Traffic Management System with an Anti Theft Scheme Dr.K.R.Kashwan
26 Surendar P Vehicle License Plate Identification System Using Aritifical Neural Network And Image Processing Techniques. Dr.R.S.Sabeenian
27 Vinothini M Design and Analysis of Cyclic Redundancy Check (CRC) Using Quantum-Dot Cellular Automata Mrs.V.Meenakshi