Date/Time
Date(s) - 04/10/2023 - 05/10/2023
9:00 am - 5:00 pm
Location
VLSI Laboratory
Categories
The department of ECE has organized two days hands-on-training in “ASIC Design Flow using Mentor Graphics EDA Tool” on 04.10.2023 and 05.10.2023. The event was held at VLSI Lab from 09.30 AM to 04.30 PM for the two days.
Event was conducted for the benefit of second, third and final year students. The resource person was Mr.K.A.Vinnalan, Application Engineer, CoreEl Technologies, Bengaluru. He emphasized the importance of Siemens for various VLSI applications and also mentioned the opportunities provided by various industries for qualified engineering graduates. He continued the event with hands-on-training in Siemens tool.
The hands-on-training was elaborated with concepts on
Day 1: Schematic Entry Layout Design, Physical Verification
Day 2: Design Entry, Synthesis, TCL Scripting for a Digital Circuit, Placement and Routing, Power Analysis.
