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Date(s) - 29/06/2020
9:30 am - 11:30 am



The department of ECE organized webinar on “FPGA design flow using XILINX VIVADO for DSP applications ” on 29-6-2020, from 9.30 AM to 11:30AM. The resource person Mr. V. Vijendra, Application Engineer, coreEl technologies,  bangalore had delivered webinar through microsoft team meet. Around 50 participants and organizers are attended the event.


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