Date/Time
Date(s) - 18/04/2023 - 19/04/2023
9:30 am - 4:30 pm
Location
VLSI Lab
Categories
The department of ECE has organized two days hands-on-training in “ASIC Design Flow using Mentor Graphics EDA Tool” on 18.04.2023 and 19.04.2023. The event was held at VLSI Lab from 09.30 AM to 04.30 PM for the two days.
Event was conducted for the benefit of third and final year ECE and EEE students. The resource person was Mr.K.A.Vinnalan, Application Engineer, CoreEl Technologies, Bengaluru. He emphasized the importance of Mentor Graphics for various VLSI applications and also mentioned the opportunities provided by various industries for qualified engineering graduates. He continued the event with hands-on-training in Mentor Graphics tool.
The hands-on-training was elaborated with concepts on
Day 1: Schematic Entry Layout Design, Physical Verification
Day 2: Design Entry, Synthesis using Leonardo, TCL Scripting for a Digital Circuit, Placement and Routing, Power Analysis.
