Date/Time
Date(s) - 08/08/2024 - 09/08/2024
9:30 am - 5:00 pm
Location
VLSI Laboratory
Categories
The department of ECE has organized two days workshop on “Digital Circuit Design & Testing using Siemens EDA – Tessent Tool” on 08.08.2024 and 09.08.2024. The event was held at VLSI Lab from 09.30 AM to 05.00 PM for the two days.
The event, designed to benefit third and final-year ECE students, featured Mr. K.A. Vinnalan, Application Engineer from CoreEl Technologies, Bengaluru, as the resource person. The program commenced with an overview of Mentor Graphics, emphasizing its crucial role in various VLSI applications. Mr. Vinnalan also shed light on the opportunities awaiting engineering graduates in different industries. Subsequently, the event seamlessly transitioned into practical, hands-on training with Mentor Graphics tools. The hands-on-training was elaborated with concepts on
Day 1:
- Introduction to ASIC (Application-Specific Integrated Circuit)
- Discussed the design flow process
- Introduction to Siemens EDA (Electronic Design Automation) tool
- Created a CMOS inverter schematic diagram
Day 2:
- Overview of CMOS inverter layout design
- Comparison between ASIC and FPGA (Field-Programmable Gate Array)
- Explored various topics in Verilog HDL (Hardware Description Language)
